module Addr(
  input         clock,
  input         reset,
  input         io_in_sf,
  input  [63:0] io_in_x,
  input  [63:0] io_in_y,
  input         io_in_carryIn,
  input         io_calEn_extRegEn,
  input         io_calEn_shiftRegEn,
  input         io_calEn_shiftInstrEn,
  input         io_calEn_shiftRegType0,
  input         io_calEn_shiftRegType1,
  input         io_calEn_shiftRegType1Long,
  input         io_calEn_shiftRegType2,
  input         io_calEn_condEn,
  input         io_calEn_addrP0En,
  input         io_calEn_addrP1En,
  input         io_calEn_bitMaskEn,
  input         io_calEn_andP0En,
  input         io_calEn_andP1En,
  input         io_calEn_orP0En,
  input         io_calEn_orP1En,
  input         io_calEn_xorP0En,
  input         io_calEn_xorP1En,
  input  [2:0]  io_calEn_movSelEn,
  input         io_calEn_bfmEn,
  input         io_calEn_bfmSign,
  input  [4:0]  io_calEn_miscSelEn,
  output [63:0] io_result,
  output        io_pstate_n,
  output        io_pstate_z,
  output        io_pstate_c,
  output        io_pstate_v
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
  reg  sfReg; // @[Addr.scala 32:22]
  reg  addrP1EnReg; // @[Addr.scala 34:28]
  wire  sf = addrP1EnReg ? sfReg : io_in_sf; // @[Addr.scala 37:15]
  wire [64:0] _unsigned_sum_T = io_in_x + io_in_y; // @[Addr.scala 40:27]
  wire [64:0] _GEN_0 = {{64'd0}, io_in_carryIn}; // @[Addr.scala 40:32]
  wire [65:0] _unsigned_sum_T_1 = _unsigned_sum_T + _GEN_0; // @[Addr.scala 40:32]
  wire [32:0] _unsigned_sum_T_4 = io_in_x[31:0] + io_in_y[31:0]; // @[Addr.scala 40:59]
  wire [32:0] _GEN_1 = {{32'd0}, io_in_carryIn}; // @[Addr.scala 40:77]
  wire [33:0] _unsigned_sum_T_5 = _unsigned_sum_T_4 + _GEN_1; // @[Addr.scala 40:77]
  wire [65:0] _unsigned_sum_T_6 = sf ? _unsigned_sum_T_1 : {{32'd0}, _unsigned_sum_T_5}; // @[Addr.scala 40:20]
  wire [64:0] _signed_sum_T_2 = $signed(io_in_x) + $signed(io_in_y); // @[Addr.scala 44:26]
  wire [1:0] _GEN_2 = {{1'd0}, io_in_carryIn}; // @[Addr.scala 44:49]
  wire  _signed_sum_T_4 = _GEN_2 == 2'h1; // @[Addr.scala 44:62]
  wire [64:0] _GEN_3 = {65{_signed_sum_T_4}}; // @[Addr.scala 44:38]
  wire [65:0] _signed_sum_T_5 = $signed(_signed_sum_T_2) + $signed(_GEN_3); // @[Addr.scala 44:38]
  wire [31:0] _signed_sum_half_T_1 = io_in_x[31:0]; // @[Addr.scala 45:36]
  wire [31:0] _signed_sum_half_T_3 = io_in_y[31:0]; // @[Addr.scala 45:61]
  wire [32:0] _signed_sum_half_T_4 = $signed(_signed_sum_half_T_1) + $signed(_signed_sum_half_T_3); // @[Addr.scala 45:43]
  wire [32:0] _GEN_5 = {33{_signed_sum_T_4}}; // @[Addr.scala 45:68]
  wire [33:0] _signed_sum_half_T_7 = $signed(_signed_sum_half_T_4) + $signed(_GEN_5); // @[Addr.scala 45:68]
  wire [64:0] unsigned_sum = _unsigned_sum_T_6[64:0]; // @[Addr.scala 39:26 40:15]
  wire [63:0] _io_pstate_v_T_1 = unsigned_sum[63:0]; // @[Addr.scala 51:50]
  wire [64:0] signed_sum = _signed_sum_T_5[64:0]; // @[Addr.scala 42:24 44:14]
  wire [64:0] _GEN_7 = {{1{_io_pstate_v_T_1[63]}},_io_pstate_v_T_1}; // @[Addr.scala 51:56]
  wire [31:0] _io_pstate_v_T_4 = unsigned_sum[31:0]; // @[Addr.scala 51:97]
  wire [32:0] signed_sum_half = _signed_sum_half_T_7[32:0]; // @[Addr.scala 43:29 45:18]
  wire [32:0] _GEN_9 = {{1{_io_pstate_v_T_4[31]}},_io_pstate_v_T_4}; // @[Addr.scala 51:103]
  assign io_result = sf ? unsigned_sum[63:0] : {{32'd0}, unsigned_sum[31:0]}; // @[Addr.scala 47:17]
  assign io_pstate_n = sf ? unsigned_sum[63] : unsigned_sum[31]; // @[Addr.scala 49:19]
  assign io_pstate_z = sf ? unsigned_sum[63:0] == 64'h0 : unsigned_sum[31:0] == 32'h0; // @[Addr.scala 50:19]
  assign io_pstate_c = sf ? unsigned_sum[64] : unsigned_sum[32]; // @[Addr.scala 48:19]
  assign io_pstate_v = sf ? $signed(_GEN_7) != $signed(signed_sum) : $signed(_GEN_9) != $signed(signed_sum_half); // @[Addr.scala 51:19]
  always @(posedge clock) begin
    if (reset) begin // @[Addr.scala 32:22]
      sfReg <= 1'h0; // @[Addr.scala 32:22]
    end else begin
      sfReg <= io_in_sf; // @[Addr.scala 33:9]
    end
    if (reset) begin // @[Addr.scala 34:28]
      addrP1EnReg <= 1'h0; // @[Addr.scala 34:28]
    end else begin
      addrP1EnReg <= io_calEn_addrP1En; // @[Addr.scala 35:15]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  sfReg = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  addrP1EnReg = _RAND_1[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
